System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-259
ID021414 Non-Confidential
4.5.64 Memory Attribute Indirection Registers 0 and 1
The MAIR0 and MAIR1 characteristics are:
Purpose To provide the memory attribute encodings corresponding to the possible
AttrIndx values in a Long-descriptor format translation table entry for
stage 1 translations.
Usage constraints These registers are accessible as follows:
Accessible only when using the Long-descriptor translation table format.
When using the Short-descriptor format see, instead, Primary Region
Remap Register on page 4-256 and Normal Memory Remap Register on
page 4-262.
AttrIndx[2], from the translation table descriptor, selects the appropriate
MAIR: setting AttrIndx[2] to 0 selects MAIR0.
The Secure copy of the register gives the value for memory accesses from
Secure state.
The Non-secure copy of the register gives the value for memory accesses
from Non-secure states other than Hyp mode.
Configurations MAIR0 (NS) is architecturally mapped to AArch64 register
MAIR_EL1[31:0] when TTBCR.EAE==1. See Memory Attribute
Indirection Register, EL1 on page 4-116.
MAIR0 (S) is mapped to AArch64 register MAIR_EL3[31:0] when
TTBCR.EAE==1. See Memory Attribute Indirection Register, EL3 on
page 4-118.
There are separate Secure and Non-secure copies of this register.
MAIR0 has write access to the Secure copy of the register disabled when
the CP15SDISABLE signal is asserted HIGH.
Attributes MAIR0 is a 32-bit register when TTBCR.EAE==1.
Figure 4-134 shows the MAIR0 and MAIR1 bit assignments.
Figure 4-134 MAIR0 and MAIR1 bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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