System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-262
ID021414 Non-Confidential
4.5.65 Normal Memory Remap Register
The NMRR characteristics are:
Purpose Provides additional mapping controls for memory regions that are mapped
as Normal memory by their entry in the PRRR.
Usage constraints This register is accessible as follows:
The register is:
• Used in conjunction with the PRRR.
• Not accessible when using the Long-descriptor translation table
format.
Configurations There are separate Secure and Non-secure copies of this register.
The Non-secure NMRR is architecturally mapped to the AArch64
MAIR_EL1[63:32] register when TTBCR.EAE==0.
The Secure NMRR is mapped to the AArch64 MAIR_EL3[63:32] register
when TTBCR.EAE==0.
NMRR has write access to the Secure copy of the register disabled when
the CP15SDISABLE signal is asserted HIGH.
NMRR has write access to the Secure copy of the register disabled when
the CP15SDISABLE signal is asserted HIGH.
Attributes NMRR is a 32-bit register when TTBCR.EAE is 0.
Figure 4-135 shows the NMRR bit assignments.
Figure 4-135 NMRR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
31 30 29 28 27 26 25 24 23 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IR0IR1IR7 IR6 IR5 IR4 IR3 IR2
22 21
OR0OR1OR7 OR6 OR5 OR4 OR3 OR2
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