System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-263
ID021414 Non-Confidential
Table 4-237 shows the NMRR bit assignments.
To access the NMRR:
MRC p15, 0, <Rt>, c10, c2, 1 ; Read NMRR into Rt
MCR p15, 0, <Rt>, c10, c2, 1 ; Write Rt to NMRR
4.5.66 Auxiliary Memory Attribute Indirection Register 0
The processor does not implement AMAIR0, so this register is always
RES0.
4.5.67 Auxiliary Memory Attribute Indirection Register 1
The processor does not implement AMAIR1, so this register is always
RES0.
4.5.68 Hyp Auxiliary Memory Attribute Indirection Register 0
The processor does not implement HAMAIR0, so this register is always
RES0.
4.5.69 Hyp Auxiliary Memory Attribute Indirection Register 1
The processor does not implement HAMAIR1, so this register is always
RES0.
4.5.70 Vector Base Address Register
The VBAR characteristics are:
Purpose Holds the exception base address for exceptions that are not taken to
Monitor mode or to Hyp mode when high exception vectors are not
selected.
Usage constraints This register is accessible as follows:
Table 4-237 NMRR bit assignments
Bits Name Description
[2n+17:2n+16]
a
ORn Outer Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory
by the PRRR.TRn entry. n is the value of the TEX[0], C and B bits, see Table 4-232 on page 4-258. The
possible values of this field are:
0b00
Region is Non-cacheable.
0b01
Region is Write-Back, Write-Allocate.
0b10
Region is Write-Through, no Write-Allocate.
0b11
Region is Write-Back, no Write-Allocate.
[2n+1:2n]
a
IRn Inner Cacheable property mapping for memory attributes n, if the region is mapped as Normal Memory
by the PRRR.TRn entry. n is the value of the TEX[0], C and B bits, see Table 4-232 on page 4-258. The
possible values of this field are the same as those given for the ORn field.
a. Where n is 0-7.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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