System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-264
ID021414 Non-Confidential
Software must program the Non-secure copy of the register with the
required initial value as part of the processor boot sequence.
Configurations There are separate Secure and Non-secure copies of this register.
The Non-secure VBAR is architecturally mapped to the AArch64
VBAR_EL1 register. See Vector Base Address Register, EL2 on
page 4-120.
The Secure VBAR is mapped to AArch64 register VBAR_EL3[31:0]. See
Vector Base Address Register, EL3 on page 4-121.
VBAR has write access to the Secure copy of the register disabled when
the CP15SDISABLE signal is asserted HIGH.
Attributes VBAR is a 32-bit register.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for
more information.
To access the VBAR:
MRC p15, 0, <Rt>, c12, c0, 0 ; Read VBAR into Rt
MCR p15, 0, <Rt>, c12, c0, 0 ; Write Rt to VBAR
4.5.71 Reset Management Register
The RMR characteristics are:
Purpose Controls the execution state that the processor boots into and allows
request of a warm reset.
Usage constraints This register is accessible as follows:
This register is subject to CP15SDISABLE, that prevents writing to this
register when the CP15SDISABLE signal is asserted.
Configurations The RMR is architecturally mapped to the AArch64 RMR_EL3 register.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes RMR is a 32-bit register.
Figure 4-136 shows the RMR bit assignments.
Figure 4-136 RMR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-----RW RW
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