System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-265
ID021414 Non-Confidential
Table 4-238 shows the RMR bit assignments.
To access the RMR:
MRC p15,0,<Rt>,c12,c0,2 ; Read RMR into Rt
MCR p15,0,<Rt>,c12,c0,2 ; Write Rt to RMR
Register access is encoded as follows:
4.5.72 Interrupt Status Register
The ISR characteristics are:
Purpose Shows whether an IRQ, FIQ, or external abort is pending. An indicated
pending abort might be a physical abort or a virtual abort.
Usage constraints This register is accessible as follows:
Configurations ISR is architecturally mapped to AArch64 register ISR_EL1. See
Interrupt Status Register on page 4-123.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes ISR is a 32-bit register.
Figure 4-137 on page 4-266 shows the ISR bit assignments.
Table 4-238 RMR bit assignments
Bits Name Function
[31:2] - Reserved,
RES0.
[1] RR Reset Request. The possible values are:
0
This is the reset value.
1
Requests a warm reset. This bit is set to 0 by either a cold or warm reset.
The bit is strictly a request.
The RR bit drives the WARMRSTREQ output signal.
[0]
AA64
a
Determines which execution state the processor boots into after a warm reset. The possible values are:
0
AArch32 Execution state.
1
AArch64 Execution state.
The reset vector address on reset takes a choice between two values, depending on the value in the AA64 bit. This
ensures that even with reprogramming of the AA64 bit, it is not possible to change the reset vector to go to a
different location.
a. The cold reset value depends on the AA64nAA32 signal.
Table 4-239 ISR access encoding
coproc opc1 CRn CRm opc2
1111 000 1100 0000 010
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
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