ARM Cortex-A53 MPCore - Page 327

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-266
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Figure 4-137 ISR bit assignments
Table 4-240 shows the ISR bit assignments.
To access the ISR:
MRC p15, 0, <Rt>, c12, c1, 1; Read ISR into Rt
Register access is encoded as follows:
4.5.73 Hyp Vector Base Address Register
The HVBAR characteristics are:
Purpose Holds the exception base address for any exception that is taken to Hyp
mode.
Usage constraints This register is accessible as follows:
Configurations The HVBAR is:
• Architecturally mapped to the AArch64 VBAR_EL2[31:0]. See
Vector Base Address Register, EL2 on page 4-120.
31 98765
0
RES
0FIA
RES
0
Table 4-240 ISR bit assignments
Bits Name Function
[31:9] - Reserved,
RES0.
[8] A External abort pending bit:
0 No pending external abort.
1 An external abort is pending.
[7] I IRQ pending bit. Indicates whether an IRQ interrupt is pending:
0 No pending IRQ.
1 An IRQ interrupt is pending.
[6] F FIQ pending bit. Indicates whether an FIQ interrupt is pending:
0 No pending FIQ.
1 An FIQ interrupt is pending.
5:0] - Reserved,
RES0.
Table 4-241 ISR access encoding
coproc opc1 CRn CRm opc2
1111 000 1100 0001 000
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -