System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-274
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations The CPUMERRSR is:
• Architecturally mapped to the AArch64 CPUMERRSR_EL1
register. See CPU Memory Error Syndrome Register on page 4-129.
• There is one copy of this register that is used in both Secure and
Non-secure states.
• A write of any value to the register updates the register to
0
.
Attributes CPUMERRSR is a a 64-bit register.
Figure 4-143 on page 4-276 shows the CPUMERRSR bit assignments.
Figure 4-142 CPUMERRSR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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