ARM Cortex-A53 MPCore - Page 336

System Control
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Table 4-247 on page 4-277 shows the CPUMERRSR bit assignments.
Note
• A fatal error results in the RAMID, Way, and RAM address recording the fatal error, even
if the sticky bit is set.
Table 4-246 CPUMERRSR bit assignments
Bits Name Function
[63] Fatal Fatal bit. This bit is set to 1 on the first memory error that caused a data abort. It is a sticky bit so that after
it is set, it remains set until the register is written.
The reset value is 0.
[62:48] - Reserved,
RES0.
[47:40] Other error
count
This field is set to 0 on the first memory error and is incremented on any memory error that does not match
the RAMID and Bank/Way information in this register while the sticky Valid bit is set.
The reset value is 0.
[39:32] Repeat error
count
This field is set to 0 on the first memory error and is incremented on any memory error that exactly
matches the RAMID and Bank/Way information in this register while the sticky Valid bit is set.
The reset value is 0.
[31] Valid Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, it remains set
until the register is written.
The reset value is 0.
[30:24] RAMID RAM Identifier. Indicates the RAM in which the first memory error. The possible values are:
0x00 L1 Instruction tag RAM.
0x01 L1 Instruction data RAM.
0x08 L1 Data tag RAM.
0x09 L1 Data data RAM.
0x0A L1 Data dirty RAM.
0x18 TLB RAM.
[23:21] - Reserved,
RES0.
[20:18] CPUID/Way Indicates the RAM where the first memory error occurred.
L1 I-tag RAM
0x0 Way 0
0x1 Way 1
0x2 - 0x7 Unused
L1 I-data RAM
0x0 Bank 0
0x1 Bank 1
0x2 - 0x7 Unused
TLB RAM
0x0 Way 0
0x1 Way 1
0x2 Way 2
0x3 Way 3
0x4 - 0x7 Unused
L1 D-dirty RAM
0x0 Dirty
RAM
0x1 - 0x7 Unused
L1 D-tag RAM
0x0 Way 0
0x1 Way 1
0x2 Way 2
0x3 Way 3
0x4 - 0x7 Unused
L1 D-data RAM
0x0 Way0-Bank0
0x1 Way0-Bank1
0x2 Way1-Bank0
0x3 Way1-Bank1
...
0x7 Way3-Bank1
[17:12] Reserved,
RES0.
[11:0] RAM address Indicates the index address of the first memory error.