System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-276
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• Only L1 Data data and L1 Data dirty RAMs can signal fatal errors, because all other RAM
instances are protected only by parity.
• If two or more memory errors in the same RAM occur in the same cycle, only one error
is reported.
• If two or more first memory error events from different RAMs occur in the same cycle,
one of the errors is selected arbitrarily.
• If two or more memory error events from different RAMs, that do not match the RAMID,
Way, and index information in this register while the sticky Valid bit is set, occur in the
same cycle, then the Other error count field is incremented only by one.
To access the CPUMERRSR:
MRRC p15, 2, <Rt>, <Rt2>, c15; Read CPUMERRSR into Rt and Rt2
MCRR p15, 2, <Rt>, <Rt2>, c15; Write Rt and Rt2 to CPUMERRSR
4.5.79 L2 Memory Error Syndrome Register
The L2MERRSR characteristics are:
Purpose Holds ECC errors on the:
• L2 data RAMs.
• L2 tag RAMs.
• SCU snoop filter RAMs.
Usage constraints This register is accessible as follows:
Configurations The L2MERRSR is:
• Architecturally mapped to the AArch64 L2MERRSR_EL1 register.
See L2 Memory Error Syndrome Register on page 4-132.
• There is one copy of this register that is used in both Secure and
Non-secure states.
• A write of any value to the register updates the register to
0x10000000.
Attributes L2MERRSR is a a 64-bit register.
Figure 4-143 shows the L2MERRSR bit assignments.
Figure 4-143 L2MERRSR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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