ARM Cortex-A53 MPCore - Page 339

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-278
ID021414 Non-Confidential
• If two or more memory error events from different RAMs, that do not match the RAMID,
bank, way, or index information in this register while the sticky Valid bit is set, occur in
the same cycle, the Other error count field is incremented only by one.
To access the L2MERRSR:
MRRC p15, 3, <Rt>, <Rt2>, c15; Read L2MERRSR into Rt and Rt2
MCRR p15, 3, <Rt>, <Rt2>, c15; Write Rt and Rt2 to L2MERRSR
4.5.80 Configuration Base Address Register
The CBAR characteristics are:
Purpose Holds the physical base address of the memory-mapped GIC CPU
interface registers.
Usage constraints This register is accessible as follows:
Configurations The CBAR is Common to the Secure and Non-secure states.
Attributes CBAR is a 32-bit register.
Figure 4-144 shows the CBAR bit assignments.
Figure 4-144 CBAR bit assignments
Table 4-248 shows the CBAR bit assignments.
To access the CBAR:
MRC p15, 1, <Rt>, c15, c3, 0; Read CBAR into Rt
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
31 8 7 0
RES0PERIPHBASE[31:18] PERIPHBASE[39:32]
1718
Table 4-248 CBAR bit assignments
Bits Name Function
[31:18] PERIPHBASE[31:18] The input PERIPHBASE[31:18] determines the reset value.
[17:8] - Reserved,
RES0.
[7:0] PERIPHBASE[39:32] The input PERIPHBASE[39:32] determines the reset value.