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ARM Cortex-A53 MPCore - Page 340

ARM Cortex-A53 MPCore
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ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 5-1
ID021414 Non-Confidential
Chapter 5
Memory Management Unit
This chapter describes the Memory Management Unit (MMU). It contains the following
sections:
About the MMU on page 5-2.
TLB organization on page 5-3.
TLB match process on page 5-4.
External aborts on page 5-5.

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