ARM Cortex-A53 MPCore - Page 354

Level 1 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-10
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6.5.2 ACE transactions
Table 6-2 shows the ACE transactions that each type of memory access generates.
See the ARM
®
AMBA
®
AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE
and ACE-Lite for more information about ACE transactions.
Table 6-2 ACE transactions
Attributes ACE transaction
Memory type Shareability Domain Load Store
Load
exclusive
Store
exclusive
Device - System ReadNoSnoop WriteNoSnoop ReadNoSnoop
and
ARLOCKM
set to HIGH
WriteNoSnoop
and
AW LO CK M
set to HIGH
Normal, inner
Non-cacheable, outer
Non-cacheable
Non-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop
and
ARLOCKM
set to HIGH
WriteNoSnoop
and
AW LO CK M
set to HIGH
Inner-shared
Outer-shared
Normal, inner
Non-cacheable, outer
Write-Back or
Write-Through, or
Normal, inner
Write-Through, outer
Write-Back,
Write-Through or
Non-cacheable, or
Normal inner
Write-Back outer
Non-cacheable or
Write-Through
Non-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop ReadNoSnoop
Inner-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop
with
ARLOCKM
set to HIGH
WriteNoSnoop
with
ARLOCKM
set to HIGH
Outer-shared System
Normal, inner
Write-Back, outer
Write-Back
Non-shared Non-shareable ReadNoSnoop WriteNoSnoop ReadNoSnoop WriteNoSnoop
Inner-shared Inner Shareable ReadShared ReadUnique or
CleanUnique if
required, then a
WriteBack
when the line is
evicted
ReadShared
with
ARLOCKM
set to HIGH
CleanUnique
with
ARLOCKM
set to HIGH if
required, then a
WriteBack
when the line is
evicted
Outer-shared Outer Shareable