ARM Cortex-A53 MPCore - Page 355

Level 1 Memory System
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6.5.3 CHI transactions
Table 6-3 shows the CHI transactions that each type of memory access generates.
See the ARM
®
AMBA
®
5 CHI Protocol Specification for more information about CHI
transactions.
Table 6-3 CHI transactions
Attributes CHI transaction
Memory type Shareability SnpAttr Load Store
Load
exclusive
Store
exclusive
Device - Non-snoopable ReadNoSnp WriteNoSnp ReadNoSnp
and Excl set to
HIGH
WriteNoSnp
and Excl set to
HIGH
Normal, inner
Non-cacheable, outer
Non-cacheable
Non-shared Non-snoopable ReadNoSnp WriteNoSnp ReadNoSnp
and Excl set to
HIGH
WriteNoSnp
and Excl set to
HIGH
Inner-shared
Outer-shared
Normal, inner
Non-cacheable, outer
Write-Back or
Write-Through, or
Normal, inner
Write-Through,
outer Write-Back,
Write-Through or
Non-cacheable, or
Normal inner
Write-Back outer
Non-cacheable or
Write-Through
Non-shared Non-snoopable ReadNoSnp WriteNoSnp ReadNoSnp ReadNoSnp
Inner-shared Non-snoopable ReadNoSnp WriteNoSnp ReadNoSnp
with Excl set to
HIGH
WriteNoSnp
with Excl set to
HIGH
Outer-shared Non-snoopable
Normal, inner
Write-Back, outer
Write-Back
Non-shared Non-snoopable ReadNoSnp WriteNoSnp ReadNoSnp WriteNoSnp
Inner-shared Inner snoopable ReadShared ReadUnique,
CleanUnique, or
MakeUnique if
allocating into
the cache, then a
WriteBackFull
when the line is
evicted.
WriteUniqueFull
or
WriteUniquePtl
if not allocating
into the cache.
ReadShared
with Excl set to
HIGH
CleanUnique
with Excl set to
HIGH if
required, then a
WriteBackFull
when the line is
evicted
Outer-shared Outer snoopable