ARM Cortex-A53 MPCore - Page 36

Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-13
ID021414 Non-Confidential
Figure 2-7 CNTCLKEN with CLKIN:CNTCLK ratio changing from 3:1 to 1:1
Note
Figure 2-7 shows the timing relationship between the system counter clock, CLKIN and
CNTCLKEN, where CNTCLKEN asserts one clock cycle before the rising edge of CLKIN.
It is important that the relationship between CLKIN and CNTCLKEN is maintained.
2.3.2 Input synchronization
The Cortex-A53 processor synchronizes the input signals:
• nCORERESET.
• nCPUPORESET.
• nFIQ.
• nIRQ.
• nL2RESET.
• nMBISTRESET.
• nPRESETDBG.
• nREI.
• nSEI.
• nVFIQ.
• nVIRQ.
• nVSEI.
• CLREXMONREQ.
• CPUQREQn.
• CTICHIN.
• CTICHOUTACK.
• CTIIRQACK.
• DBGEN.
• EDBGRQ.
• EVENTI.
• L2FLUSHREQ.
• L2QREQn.
• NEONQREQn.
• NIDEN.
• SPIDEN.
• SPNIDEN.
CNTCLK
CNTCLKEN asserts one CLKIN
cycle before the rising edge of
CNTCLK
1 CLKIN
cycle
CLKIN:CNTCLK = 3:1 CLKIN:CNTCLK = 1:1
CNTCLKEN
CLKIN
1 CLKIN
cycle