ARM Cortex-A53 MPCore - Page 37

Functional Description
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The SoC can present these inputs asynchronously. All other external signals must be
synchronous with reference to CLKIN.
Note
The synchronised CTICHIN input signals are used only if the CISBYPASS input signal is
deasserted LOW. If the CISBYPASS signal is asserted HIGH the CTICHIN synchronizers are
not used, and the SoC must present the CTICHIN synchronously to CLKIN.
2.3.3 Resets
The Cortex-A53 processor has the following active-LOW reset input signals:
nCPUPORESET[CN:0]
Where CN is the number of cores minus one.
These primary, cold reset signals initialize all resettable registers in the
corresponding core, including debug registers and ETM registers.
nCORERESET[CN:0]
These primary reset signals initialize all resettable registers in the
corresponding core, not including debug registers and ETM registers.
nPRESETDBG This single, cluster-wide signal resets the integrated CoreSight
components that connect to the external PCLK domain, such as debug
logic.
nL2RESET This single, cluster-wide signal resets all resettable registers in the L2
memory system and the logic in the SCU.
nMBISTRESET An external MBIST controller can use this signal to reset the entire SoC.
The nMBISTRESET signal resets all resettable registers in the cluster,
for entry into, and exit from, MBIST mode.
All of these resets can be asynchronously:
• Asserted, HIGH to LOW.
• Deasserted, LOW to HIGH.
Reset synchronisation logic inside the Cortex-A53 processor ensures that reset deassertion is
synchronous for all resettable registers. The processor clock is not required for reset assertion,
but the processor clock must be present for reset deassertion to ensure reset synchronisation.
In general, you only have to hold reset signals active for three processor clock cycles for the
reset to take effect. However, you must hold the reset signal LOW until the power returns and
the unit or processor is ready for the reset to take effect if:
• The Advanced SIMD and Floating-point unit of a core undergoing a reset is in retention
state.
• A core that is being reset is in retention state.
This is the responsibility of the system implementer, because the time taken for retention exit
and the behavior of the power controller varies by partner and by implementation.
Table 2-1 on page 2-15 describes the valid reset signal combinations. All other combinations of
reset signals are illegal. In the table, n designates the core that is reset.