Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-15
ID021414 Non-Confidential
Table 2-1 Valid reset combinations
Reset combination Signals Value Description
Cluster cold reset nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 0
a
all = X
a
0
0
1
All logic is held in reset.
Cluster cold reset with debug active nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 0
a
all = X
a
1
0
1
All cores are held in reset so they can be powered up.
The L2 is held in reset, but must remain powered up.
This enables external debug over power down for the
cluster.
Individual core cold reset with
debug active
nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
[n] = 0
a
[n] = X
a
1
1
1
Individual core is held in reset, so that the core can be
powered up. This enables external debug over power
down for the core that is held in reset.
Individual core warm reset with
trace and debug active
nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
[n] = 1
[n] = 0
1
1
1
Individual core is held in reset.
Debug logic reset nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 1
all = 1
0
1
1
Cluster debug logic is held in reset.
MBIST reset nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 1
all = 1
1
1
0
All logic is held in reset.
Normal state nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 1
all = 1
1
1
1
No logic is held in reset.
a. For cold reset, nCPUPORESET must be asserted. nCORERESET can be asserted, but is not required.
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