Level 1 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-17
ID021414 Non-Confidential
The TLB RAM contains the data for the main TLB, the walk cache, and the Intermediate
Physical Address (IPA) cache RAMs. Table 6-12 shows the TLB indexes that determines the
format of the TLB RAM accesses.
Main TLB RAM
The main TLB RAM uses a 117-bit encoding:
Data Register 0[31:0] TLB Descriptor[31:0].
Data Register 1[31:0] TLB Descriptor[63:32].
Data Register 2[31:0] TLB Descriptor[95:64].
Data Register 3[20:0] TLB Descriptor[116:96].
Table 6-13 shows the data fields in the TLB descriptor.
Table 6-12 TLB RAM format
TLB index[7:0] Format
0-127 Main TLB RAM, see Main TLB RAM
128-143 Walk cache RAM, see Walk cache RAM on page 6-20
144-159 IPA cache RAM, see IPA cache RAM on page 6-21
160-255 Unused
Table 6-13 Main TLB descriptor data fields
Bits Name Description
[116:114] Parity ECC inclusion is processor configuration dependent. If ECC is not configured, these
bits are absent.
[113:112] S2 Level The stage 2 level that gave this translation:
0b00
No stage 2 translation performed.
0b01
Level 1.
0b10
Level 2.
0b11
Level 3.
[111:109] S1 Size The stage 1 size that gave this translation:
0b000
4KB.
0b001
64KB.
0b010
1MB.
0b011
2MB.
0b100
16MB.
0b101
512MB.
0b110
1GB.
[108:105] Domain Valid only if the entry was fetched in VMSAv7 format.
[104:97] Memory Type and shareability See Table 6-14 on page 6-18.
[96] XS2 Stage2 executable permissions.
[95] XS1Nonusr Non user mode executable permissions.
[94] XS1Usr User mode executable permissions.
[93:66] PA Physical Address.
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