ARM Cortex-A53 MPCore

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Level 2 Memory System

ID021414 Non-Confidential

7.3.4 Read response

The ACE master can delay accepting a read data channel transfer by holding RREADY LOW

for an indeterminate number of cycles. RREADY can be deasserted LOW between read data

channel transfers that form part of the same transaction.

The ACE master asserts the read acknowledge signal RACK HIGH in the ACLK cycle

following acceptance of the last read data channel transfer for a transaction. RACK is asserted

in AXI3 compatibility mode in addition to ACE configurations.

Note

• For interoperability of system components, ARM recommends that components

interfacing with the ACE master are fully ACE compliant with no reliance on the subset

of permitted RACK behavior described for the Cortex-A53 processor.

• If the interconnect does not perform hazarding between coherent and non-coherent

requests, then, after it has returned the first transfer of read data for a non-coherent read,

it must return all the remaining read transfers in the transaction, without requiring

progress of any snoops to the cluster that could be to the same address.

7.3.5 Write response

The ACE master requires that the slave does not return a write response until it has received the

write address.

The ACE master always accepts write responses without delay by holding BREADY HIGH.

The ACE master asserts the write acknowledge signal WACK HIGH in the ACLK cycle

following acceptance of a write response. WA CK is asserted in AXI3 compatibility mode in

addition to ACE configurations.

Note

For interoperability of system components, ARM recommends that components interfacing

with the ACE master are fully ACE compliant with no reliance on the subset of permitted

BREADY and WACK behavior described for the Cortex-A53 processor.

7.3.6 Barriers

The Cortex-A53 processor supports sending barrier transactions to the interconnect, or

terminating barriers within the cluster.

• To send barriers on the ACE interface, set SYSBARDISABLE to LOW.

• To terminate barriers within the cluster, set SYSBARDISABLE to HIGH.

If you terminate barriers within the cluster, ensure that your interconnect and any peripherals

connected to it do not return a write response for a transaction until that transaction would be

considered complete by a later barrier. This means that the write must be observable to all other

masters in the system. ARM expects the majority of peripherals to meet this requirement.

For best performance, ARM recommends that barriers are terminated within the cluster.

7.3.7 AXI3 compatibility mode

The Cortex-A53 processor implements an AXI3 compatibility mode that enables you to use the

processor in a standalone environment where the AMBA 4 ACE interface is not required and

the processor does not propagate barriers outside of the cluster. To enable this mode you must

ARM Cortex-A53 MPCore - Page 376