ARM Cortex-A53 MPCore - Page 377

Level 2 Memory System
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set the SYSBARDISABLE input pin to HIGH on the boundary of the processor. You must also
ensure that the BROADCASTINNER, BROADCASTOUTER, and
BROADCASTCACHEMAINT input pins are set to LOW.
7.3.8 AXI privilege information
AXI provides information about the privilege level of an access on the ARPROTM[0] and
AW P ROT M[0] signals. However, when accesses might be cached or merged together, the
resulting transaction can have both privileged and unprivileged data combined. If this happens,
the Cortex-A53 processor marks the transaction as privileged, even it if was initiated by an
unprivileged process.
Table 7-10 shows Cortex-A53 processor exception levels and corresponding ARPROTM[0]
and AW PR OT M[ 0] values.
Table 7-10 Cortex-A53 MPCore mode and ARPROT and AWPROT values
Processor exception level Type of access
Value of ARPROT[0]
and AWPROT[0]
EL0, EL1, EL2, EL3 Cacheable read access Privileged access
EL0 Device, or normal Non-cacheable read access Unprivileged access
EL1, EL2, EL3 Privileged access
EL0, EL1, EL2, EL3 Cacheable write access Privileged access
EL0 Device, nGnRnE, nGnRE, and nGRE write Unprivileged access
EL1, EL2, EL3 Privileged access
EL0 Normal Non-cacheable or Device GRE write, except for
STREX , STREXB ,
STREXH , STREXD , STXR , STXRB , STXRH , STXP , STLXR , STLXRB , STLXRH and STLXP
to shareable memory
Privileged access
EL0 Normal Non-cacheable write for
STREX , STREXB , STREXH , STREXD , STXR
STXRB , STXRH , STXP , STLXR , STLXRB , STLXRH and STLXP to shareable memory
Unprivileged access
EL1, EL2, EL3 Normal Non-cacheable write Privileged access
EL0, EL1, EL2, EL3 TLB page walk Privileged access