ARM Cortex-A53 MPCore - Page 396

Generic Interrupt Controller CPU Interface
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Table 9-6 shows the GICH_VTR bit assignments.
9.2.6 Virtual CPU interface register summary
The virtual CPU interface forwards virtual interrupts to a connected Cortex-A53 processor,
subject to the normal GIC handling and prioritization rules. The virtual interface control
registers control virtual CPU interface operation, and in particular, the virtual CPU interface
uses the contents of the List registers to determine when to signal virtual interrupts. When a core
accesses the virtual CPU interface, the List registers are updated. For more information on the
virtual CPU interface, see the ARM
®
Generic Interrupt Controller Architecture Specification.
Table 9-7 describes the registers for the virtual CPU interface.
All the registers in Table 9-7 are word-accessible. Registers not described in this table are
RES0.
See the ARM
®
Generic Interrupt Controller Architecture Specification for more information.
Table 9-6 GICH_VTR bit assignments
Bit Name Description
[31:29] PRIbits Indicates the number of priority bits implemented, minus one:
0x4 Five bits of priority and 32 priority levels.
[28:26] PREbits Indicates the number of preemption bits implemented, minus one:
0x4 Five bits of preemption and 32 preemption levels.
[25:6] - Reserved,
RES0.
[5:0] ListRegs Indicates the number of implemented List Registers, minus one:
0x3 Four List Registers.
Table 9-7 Virtual CPU interface register summary
Name Type Reset Description
GICV_CTLR RW
0x00000000 VM Control Register
GICV_PMR RW
0x00000000 VM Priority Mask Register
GICV_BPR RW
0x00000002 VM Binary Point Register
GICV_IAR RO - VM Interrupt Acknowledge Register
GICV_EOIR WO - VM End Of Interrupt Register
GICV_RPR RO
0x000000FF VM Running Priority Register
GICV_HPPIR RO
0x000003FF VM Highest Priority Pending Interrupt Register
GICV_ABPR RW
0x00000003 VM Aliased Binary Point Register
GICV_AIAR RO - VM Aliased Interrupt Acknowledge Register
GICV_AEOIR WO - VM Aliased End of Interrupt Register
GICV_AHPPIR RO
0x000003FF VM Aliased Highest Priority Pending Interrupt Register
GICV_APR0 RW
0x00000000 VM Active Priority Register on page 9-8
GICV_IIDR RO
0x0034143B VM CPU Interface Identification Register on page 9-8
GICV_DIR WO - VM Deactivate Interrupt Register