Generic Interrupt Controller CPU Interface
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 9-8
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9.2.7 Virtual CPU interface register descriptions
This section describes only registers whose implementation is specific to the Cortex-A53
processor. All other registers are described in the ARM
®
Generic Interrupt Controller
Architecture Specification. Table 9-7 on page 9-7 provides cross-references to individual
registers.
VM Active Priority Register
The GICV_APR0 characteristics are:
Purpose For software compatibility, this register is present in the virtual CPU
interface. However, in a virtualized system, it is not used when preserving
and restoring state.
Usage constraints Reading the content of this register and then writing the same values must
not change any state because there is no requirement to preserve and
restore state during a powerdown.
Configurations Available in all configurations.
Attributes See the register summary in Table 9-7 on page 9-7.
The Cortex-A53 processor implements the GICV_APR0 as an alias of GICH_APR0.
VM CPU Interface Identification Register
The GICV_IIDR characteristics are:
Purpose Provides information about the implementer and revision of the virtual
CPU interface.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 9-7 on page 9-7.
The bit assignments for the VM CPU Interface Identification Register are identical to the
corresponding register in the CPU interface, see CPU Interface Identification Register on
page 9-5.
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