Contents
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. iv
ID021414 Non-Confidential
4.2 AArch64 register summary ...................................................................................... 4-3
4.3 AArch64 register descriptions ................................................................................ 4-14
4.4 AArch32 register summary .................................................................................. 4-135
4.5 AArch32 register descriptions .............................................................................. 4-157
Chapter 5 Memory Management Unit
5.1 About the MMU ........................................................................................................ 5-2
5.2 TLB organization ...................................................................................................... 5-3
5.3 TLB match process .................................................................................................. 5-4
5.4 External aborts ......................................................................................................... 5-5
Chapter 6 Level 1 Memory System
6.1 About the L1 memory system .................................................................................. 6-2
6.2 Cache behavior ........................................................................................................ 6-3
6.3 Support for v8 memory types ................................................................................... 6-6
6.4 L1 Instruction memory system ................................................................................. 6-7
6.5 L1 Data memory system .......................................................................................... 6-9
6.6 Data prefetching .................................................................................................... 6-12
6.7 Direct access to internal memory .......................................................................... 6-13
Chapter 7 Level 2 Memory System
7.1 About the L2 memory system .................................................................................. 7-2
7.2 Snoop Control Unit .................................................................................................. 7-3
7.3 ACE master interface ............................................................................................... 7-6
7.4 CHI master interface .............................................................................................. 7-13
7.5 Additional memory attributes ................................................................................. 7-17
7.6 Optional integrated L2 cache ................................................................................. 7-18
7.7 ACP ....................................................................................................................... 7-19
Chapter 8 Cache Protection
8.1 Cache protection behavior ....................................................................................... 8-2
8.2 Error reporting .......................................................................................................... 8-4
Chapter 9 Generic Interrupt Controller CPU Interface
9.1 About the GIC CPU Interface .................................................................................. 9-2
9.2 GIC programmers model ......................................................................................... 9-3
Chapter 10 Generic Timer
10.1 About the Generic Timer ........................................................................................ 10-2
10.2 Generic Timer functional description ..................................................................... 10-3
10.3 Generic Timer register summary ........................................................................... 10-4
Chapter 11 Debug
11.1 About debug .......................................................................................................... 11-2
11.2 Debug register interfaces ....................................................................................... 11-4
11.3 AArch64 debug register summary ......................................................................... 11-6
11.4 AArch64 debug register descriptions ..................................................................... 11-8
11.5 AArch32 debug register summary ....................................................................... 11-15
11.6 AArch32 debug register descriptions ................................................................... 11-17
11.7 Memory-mapped register summary ..................................................................... 11-21
11.8 Memory-mapped register descriptions ................................................................ 11-25
11.9 Debug events ....................................................................................................... 11-36
11.10 External debug interface ...................................................................................... 11-37
11.11 ROM table ............................................................................................................ 11-41
Chapter 12 Performance Monitor Unit
12.1 About the PMU ...................................................................................................... 12-2
12.2 PMU functional description .................................................................................... 12-3
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