ARM Cortex-A53 MPCore - Page 5

Contents
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. v
ID021414 Non-Confidential
12.3 AArch64 PMU register summary ........................................................................... 12-5
12.4 AArch64 PMU register descriptions ....................................................................... 12-7
12.5 AArch32 PMU register summary ......................................................................... 12-14
12.6 AArch32 PMU register descriptions ..................................................................... 12-16
12.7 Memory-mapped register summary ..................................................................... 12-23
12.8 Memory-mapped register descriptions ................................................................ 12-26
12.9 Events .................................................................................................................. 12-36
12.10 Interrupts .............................................................................................................. 12-40
12.11 Exporting PMU events ......................................................................................... 12-41
Chapter 13 Embedded Trace Macrocell
13.1 About the ETM ....................................................................................................... 13-2
13.2 ETM trace unit generation options and resources ................................................. 13-3
13.3 ETM trace unit functional description ..................................................................... 13-5
13.4 Reset ..................................................................................................................... 13-7
13.5 Modes of operation and execution ......................................................................... 13-8
13.6 ETM trace unit register interfaces .......................................................................... 13-9
13.7 ETM register summary ........................................................................................ 13-10
13.8 ETM register descriptions .................................................................................... 13-13
13.9 Interaction with debug and performance monitoring unit ..................................... 13-76
Chapter 14 Cross Trigger
14.1 About the cross trigger ........................................................................................... 14-2
14.2 Trigger inputs and outputs ..................................................................................... 14-3
14.3 Cortex-A53 CTM .................................................................................................... 14-4
14.4 Cross trigger register summary ............................................................................. 14-5
14.5 Cross trigger register descriptions ......................................................................... 14-8
Appendix A Signal Descriptions
A.1 About the signal descriptions ................................................................................... A-2
A.2 Clock signals ............................................................................................................ A-3
A.3 Reset signals ........................................................................................................... A-4
A.4 Configuration signals ............................................................................................... A-5
A.5 Generic Interrupt Controller signals ......................................................................... A-6
A.6 Generic Timer signals .............................................................................................. A-8
A.7 Power management signals .................................................................................... A-9
A.8 L2 error signals ...................................................................................................... A-11
A.9 ACE and CHI interface signals .............................................................................. A-12
A.10 CHI interface signals .............................................................................................. A-13
A.11 ACE interface signals ............................................................................................ A-17
A.12 ACP interface signals ............................................................................................ A-22
A.13 External debug interface ........................................................................................ A-25
A.14 ATB interface signals ............................................................................................. A-28
A.15 Miscellaneous ETM trace unit signals ................................................................... A-29
A.16 CTI interface signals .............................................................................................. A-30
A.17 PMU interface signals ............................................................................................ A-31
A.18 DFT and MBIST interface signals .......................................................................... A-32
Appendix B Cortex-A53 Processor AArch32 unpredictable Behaviors
B.1 Use of R15 by Instruction ........................................................................................ B-3
B.2 unpredictable instructions within an IT Block ........................................................... B-4
B.3 Load/Store accesses crossing page boundaries ..................................................... B-5
B.4 ARMv8 Debug unpredictable behaviors .................................................................. B-6
B.5 Other unpredictable behaviors ............................................................................... B-11
Appendix C Revisions