Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-10
ID021414 Non-Confidential
To access the DBGBCRn_EL1 in AArch64 Execution state, read or write the register with:
MRS <Xt>, DBGBCRn_EL1; Read Debug Breakpoint Control Register n
MSR DBGBCRn_EL1, <Xt>; Write Debug Breakpoint Control Register n
To access the DBGBCRn in AArch32 Execution state, read or write the CP14 register with:
MRC p14, 0, <Rt>, c0, cn, 4; Read Debug Breakpoint Control Register n
MCR p14, 0, <Rt>, c0, cn, 4; Write Debug Breakpoint Control Register n
The DBGBCRn_EL1 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x4n8
.
[8:5]
BAS
a
Byte Address Select. Defines which half-words a regular breakpoint matches, regardless of the instruction set and
execution state. A debugger must program this field as follows:
0x3
Match the T32 instruction at DBGBVRn.
0xC
Match the T32 instruction at DBGBVRn+2.
0xF
Match the A64 or A32 instruction at DBGBVRn, or context match.
All other values are reserved.
The ARMv8-A architecture does not support direct execution of Java bytecodes. BAS[3] and BAS[1] ignore
writes and on reads return the values of BAS[2] and BAS[0] respectively.
[4:3] - Reserved, RES0.
[2:1] PMC Privileged Mode Control. Determines the exception level or levels that a breakpoint debug event for breakpoint
n is generated.
This field must be interpreted with the SSC and HMC fields to determine the mode and security states that can be
tested.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for possible values of
the fields.
The value of DBGBCR.E is UNKNOWN on reset. A debugger must ensure that DBGBCR.E has a defined value
before it programs DBGDSCR.MDBGen and DBGDSCR.HDBGen to enable debug.
a. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information on how the BAS field is
interpreted by hardware.
Table 11-4 DBGBCRn_EL1 bit assignments (continued)
Bits Name Function
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