Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-19
ID021414 Non-Confidential
Table 11-9 shows the DBGDEVID bit assignments.
To access the DBGDEVID in AArch32 Execution state, read the CP14 register with:
MRC p14, 0, <Rt>, c7, c2, 7; Read Debug Device ID Register 0
11.6.3 Debug Device ID Register 1
The DBGDEVID1 characteristics are:
Purpose Adds to the information given by the DBGDIDR by describing other
features of the debug implementation.
Usage constraints This register is accessible as follows:
Configurations There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes See the register summary in Table 11-7 on page 11-15.
Figure 11-7 on page 11-20 shows the DBGDEVID1 bit assignments.
Table 11-9 DBGDEVID bit assignments
Bits Name Function
[31:28] CIDMask Specifies the level of support for the Context ID matching breakpoint masking capability. This value is:
0x0
Context ID masking is not implemented.
[27:24] AuxRegs Specifies support for the Debug External Auxiliary Control Register. This value is:
0x0
None supported.
[23:20] DoubleLock Specifies support for the Debug OS Double Lock Register. This value is:
0x1
The processor supports Debug OS Double Lock Register.
[19:16] VirExtns Specifies whether EL2 is implemented. This value is:
0x1
The processor implements EL2.
[15:12] VectorCatch Defines the form of the vector catch event implemented. This value is:
0x0
The processor implements address matching form of vector catch.
[11:8] BPAddrMask Indicates the level of support for the Immediate Virtual Address (IVA) matching breakpoint masking
capability. This value is:
0xF
Breakpoint address masking not implemented. DBGBCRn[28:24] are res0.
[7:4] WPAddrMask Indicates the level of support for the DVA matching watchpoint masking capability. This value is:
0x1
Watchpoint address mask implemented.
[3:0] PCSample Indicates the level of support for Program Counter sampling using debug registers 40 and 41. This value is:
0x3
EDPCSR, EDCIDSR and EDVIDSR are implemented as debug registers 40, 41, and 42.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
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