ARM Cortex-A53 MPCore - Page 435

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-33
ID021414 Non-Confidential
Table 11-22 shows the EDCIDR0 bit assignments.
The EDCIDR0 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFF0 .
Component Identification Register 1
The EDCIDR1 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The EDCIDR1 is in the Debug power domain.
Attributes See the register summary in Table 11-11 on page 11-21.
Figure 11-17 shows the EDCIDR1 bit assignments.
Figure 11-17 EDCIDR1 bit assignments
Table 11-23 shows the EDCIDR1 bit assignments.
The EDCIDR1 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFF4 .
Component Identification Register 2
The EDCIDR2 characteristics are:
Purpose Provides information to identify an external debug component.
Table 11-22 EDCIDR0 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] Size
0x0D Preamble byte 0.
Off DLK OSLK EDAD SLK Default
-- - - - RO
RES0
31 0
PRMBL_1
78
34
CLASS
Table 11-23 EDCIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] CLASS
0x9 Debug component.
[3:0] PRMBL_1
0x0 Preamble.