Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-34
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The EDCIDR2 is in the Debug power domain.
Attributes See the register summary in Table 11-11 on page 11-21.
Figure 11-18 shows the EDCIDR2 bit assignments.
Figure 11-18 EDCIDR2 bit assignments
Table 11-24 shows the EDCIDR2 bit assignments.
The EDCIDR2 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFF8
.
Component Identification Register 3
The EDCIDR3 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The EDCIDR3 is in the Debug power domain.
Attributes See the register summary in Table 11-11 on page 11-21.
Figure 11-19 on page 11-35 shows the EDCIDR3 bit assignments.
Off DLK OSLK EDAD SLK Default
-- - - - RO
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