Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-39
ID021414 Non-Confidential
11.10.2 DBGPWRDUP debug signal
You must set the DBGPWRDUP signal LOW before removing power to the processor domain.
After power is restored to the processor domain, the DBGPWRDUP signal must be asserted
HIGH. The EDPRSR.PU bit reflects the value of this DBGPWRDUP signal.
DBGPWRDUP must be tied HIGH if the particular implementation does not support separate
processor and SCU power domains.
11.10.3 DBGL1RSTDISABLE debug signal
When set HIGH, the DBGL1RSTDISABLE input signal disables the automatic hardware
controlled invalidation of the L1 data cache after the processor is reset, using nCORERESET
or nCPUPORESET.
The DBGL1RSTDISABLE must be used only to assist debug of an external watchdog
triggered reset by allowing the contents of the L1 data cache prior to the reset to be observable
after the reset. If reset is asserted, while an L1 data cache eviction or L1 data cache fetch is
performed, the accuracy of those cache entries is not guaranteed.
You must not use the DBGL1RSTDISABLE signal to disable automatic hardware controlled
invalidation of the L1 data cache in normal processor powerup sequences. This is because
synchronisation of the L1 data cache invalidation sequence with the duplicate L1 tags in the
SCU is not guaranteed.
The DBGL1RSTDISABLE signal applies to all cores in the cluster. Each core samples the
signal when nCORERESET or nCPUPORESET is asserted.
If the functionality offered by the DBGL1RSTDISABLE input signal is not required, the input
must be tied to LOW.
0x16000
-
0x16FFF
CPU 3 Debug
0x17000
-
0x17FFF
CPU 3 PMU
0x18000
-
0x18FFF
CPU 0 CTI
0x19000
-
0x19FFF
CPU 1 CTI
0x1A000
-
0x1AFFF
CPU 2 CTI
0x1B000
-
0x1BFFF
CPU 3 CTI
0x1C000
-
0x1CFFF
CPU 0 Trace
0x1D000
-
0x1DFFF
CPU 1 Trace
0x1E000
-
0x1EFFF
CPU 2 Trace
0x1F000
-
0x
1FFFF CPU 3 Trace
a. Indicates the mapped component if present, otherwise reserved.
Table 11-27 Address mapping for APB components (continued)
Address offset [21:0]
Component
a
To Next Page
Loading...
