Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-45
ID021414 Non-Confidential
11.11.4 Peripheral Identification Registers
The Peripheral Identification Registers provide standard information required for all
components that conform to the ARM Debug Interface v5 specification. There is a set of eight
registers, listed in register number order in Table 11-32.
Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the
eight Peripheral ID Registers define a single 64-bit Peripheral ID.
The ROM table Peripheral ID registers are:
• Peripheral Identification Register 0.
• Peripheral Identification Register 1 on page 11-46.
• Peripheral Identification Register 2 on page 11-47.
• Peripheral Identification Register 3 on page 11-47.
• Peripheral Identification Register 4 on page 11-48.
• Peripheral Identification Register 5-7 on page 11-49.
Peripheral Identification Register 0
The ROMPIDR0 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The ROMPIDR0 is in the Debug power domain.
Attributes See the register summary in Table 11-28 on page 11-41.
Figure 11-22 on page 11-46 shows the ROMPIDR0 bit assignments.
Table 11-32 Summary of the ROM table Peripheral Identification Registers
Register Value Offset
ROMPIDR4
0x04 0xFD0
ROMPIDR5
0x00 0xFD4
ROMPIDR6
0x00 0xFD8
ROMPIDR7
0x00 0xFDC
ROMPIDR0
0xA1 0xFE0
ROMPIDR1
0xB4 0xFE4
ROMPIDR2
0x2B 0xFE8
ROMPIDR3
0x00 0xFEC
Off DLK OSLK EDAD SLK Default
-- - - - RO
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