Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-46
ID021414 Non-Confidential
Figure 11-22 ROMPIDR0 bit assignments
Table 11-33 shows the ROMPIDR0 bit assignments.
The ROMPIDR0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFE0
.
Peripheral Identification Register 1
The ROMPIDR1 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The ROMPIDR1 is in the Debug power domain.
Attributes See the register summary in Table 11-28 on page 11-41.
Figure 11-23 shows the ROMPIDR1 bit assignments.
Figure 11-23 ROMPIDR1 bit assignments
Table 11-34 shows the ROMPIDR1 bit assignments.
Table 11-33 ROMPIDR0 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] Part_0 Least significant byte of the ROM table part number.
0xA1
for v8 memory map.
0xA3
for v7 memory map.
Off DLK OSLK EDAD SLK Default
-- - - - RO
Table 11-34 ROMPIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] DES_0
0xB
Least significant nibble of JEP106 ID code. For ARM Limited.
[3:0] Part_1
0x4
Most significant nibble of the ROM table part number.
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