Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-47
ID021414 Non-Confidential
The ROMPIDR1 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFE4
.
Peripheral Identification Register 2
The ROMPIDR2 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The ROMPIDR2 is in the Debug power domain.
Attributes See the register summary in Table 11-28 on page 11-41.
Figure 11-24 shows the ROMPIDR2 bit assignments.
Figure 11-24 ROMPIDR2 bit assignments
Table 11-35 shows the ROMPIDR2 bit assignments.
The ROMPIDR2 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFE8
.
Peripheral Identification Register 3
The ROMPIDR3 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Off DLK OSLK EDAD SLK Default
-- - - - RO
Table 11-35 ROMPIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] Revision
0x2
r0p2.
[3] JEDEC
0b1
RAO. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011
Designer, most significant bits of JEP106 ID code. For ARM Limited.
Off DLK OSLK EDAD SLK Default
-- - - - RO
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