Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-26
ID021414 Non-Confidential
The external agent can determine that at least one of the cores in the cluster has executed an
SEV
instruction by checking the EVENTO pin. When
SEV
is executed by any of the cores in the
cluster, an event is signaled to all the cores in the device, and the EVENTO pin is asserted. This
pin is asserted HIGH for three CLKIN clock cycles when any core in the cluster executes an
SEV
instruction.
2.4.4 Communication to the Power Management Controller
Communication between the Cortex-A53 processor and the system power management
controller can be performed using one or both of the:
• STANDBYWFI[3:0] and STANDBYWFIL2 signals.
• Q-channel on page 2-27.
STANDBYWFI[3:0] and STANDBYWFIL2 signals
The STANDBYWFI[n] signal indicates when an individual core is in idle and low power state.
The power management controller can remove power from an individual core when
STANDBYWFI[n] is asserted. See Individual core shutdown mode on page 2-21 for more
information.
The STANDBYWFIL2 signal indicates when all individual cores and the L2 memory system
are in idle and low power state. A power management controller can remove power from the
Cortex-A53 processor when STANDBYWFIL2 is asserted. See Cluster shutdown mode
without system driven L2 flush on page 2-22 and Cluster shutdown mode with system driven L2
flush on page 2-23 for more information.
The Cortex-A53 processor includes a minimal L2 memory system in configurations without an
L2 cache. Therefore, the power management controller must always wait for assertion of
STANDBYWFIL2 before removing power from the Cortex-A53 processor.
Figure 2-11 on page 2-27 shows how STANDBYWFI[3:0] and STANDBYWFIL2 correspond
to individual cores and the Cortex-A53 processor.
To Next Page
Loading...
