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ARM Cortex-A53 MPCore - Page 50

ARM Cortex-A53 MPCore
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Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-27
ID021414 Non-Confidential
Figure 2-11 STANDBYWFI[3:0] and STANDBYWFIL2 signals
Q-channel
Q-channel is a clock and power controller to device interface, to manage device quiescence. The
interface enables:
The controller to manage entry to, and exit from, a device quiescent state. Quiescence
management is typically of, but not restricted to, clock gated, and power gated retention
states, of the device or device partitions.
The capability to indicate a requirement for exit from the quiescent state. The associated
signalling can contain contributions from other devices dependent on the interfaced
device’s operations.
Optional device capability to deny a quiescence request.
Safe asynchronous interfacing across clock domains.
Cortex-A53 processor
Core 3
Level 2 memory system
Snoop Control Unit (SCU)
STANDBYWFI[3:0] STANDBYWFIL2
Core 2
Core 1
Core 0
Level 1 memory system
Data Processing Unit (DPU)

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