ARM Cortex-A53 MPCore - Page 515

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-20
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Attributes TRCEVENTCTL1R is a 32-bit RW trace register.
See the register summary in Table 13-3 on page 13-10.
Figure 13-9 shows the TRCEVENTCTL1R bit assignments.
Figure 13-9 TRCEVENTCL1R bit assignments
Table 13-10 shows the TRCEVENTCTL1R bit assignments.
The TRCEVENTCTL1R can be accessed through the internal memory-mapped interface and
the external debug interface, offset
0x024 .
13.8.8 Stall Control Register
The TRCSTALLCTLR characteristics are:
Purpose Enables the ETM trace unit to stall the Cortex-A53 processor if the ETM
trace unit FIFO overflows.
Usage constraints • You must always program this register as part of trace unit
initialization.
• Accepts writes only when the trace unit is disabled.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-10 on page 13-21 shows the TRCSTALLCTLR bit assignments.
31 0
RES
0
43587
EN
12 11 10
RES
0
ATB
13
LPOVERRIDE
Table 13-10 TRCEVENTCL1R bit assignments
Bits Name Function
[31:13] - Reserved,
RES0.
[12] LPOVERRIDE Low power state behavior override:
0 Low power state behavior unaffected.
1 Low power state behavior overridden. The resources and Event trace generation are
unaffected by entry to a low power state.
[11] ATB ATB trigger enable:
0 ATB trigger disabled.
1 ATB trigger enabled.
[10:4] - Reserved,
RES0.
[3:0] EN One bit per event, to enable generation of an event element in the instruction trace stream when the
selected event occurs:
0 Event does not cause an event element.
1 Event causes an event element.