Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-21
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Figure 13-10 TRCSTALLCTLR bit assignments
Table 13-11 shows the TRCSTALLCTLR bit assignments.
The TRCSTALLCTLR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x02c
.
13.8.9 Global Timestamp Control Register
The TRCTSCTLR characteristics are:
Purpose Controls the insertion of global timestamps in the trace streams. When the
selected event is triggered, the trace unit inserts a global timestamp into
the trace streams. The event is selected from one of the Resource
Selectors.
Usage constraints • Accepts writes only when the trace unit is disabled.
• Must be programmed if TRCCONFIGR.TS==1.
Configurations Available in all configurations.
Attributes TRCTSCTLR is a 32-bit RW trace register.
The register is set to an
UNKNOWN value on a trace unit reset. See also
Table 13-3 on page 13-10.
Figure 13-11 shows the TRCTSCTLR bit assignments:
Figure 13-11 TRCTSCTLR bit assignments
Table 13-11 TRCSTALLCTLR bit assignments
Bits Name Function
[31:9] - Reserved,
RES0.
[8] ISTALL Instruction stall bit. Controls if the trace unit can stall the processor when the instruction trace buffer space is less
than LEVEL:
0
The trace unit does not stall the processor.
1
The trace unit can stall the processor.
[7:4] - Reserved,
RES0.
[3:2] LEVEL Threshold level field. The field can support 4 monotonic levels from
0b00
to
0b11
, where:
0b00
Zero invasion. This setting has a greater risk of an ETM trace unit FIFO overflow.
0b11
Maximum invasion occurs but there is less risk of a FIFO overflow.
[1:0] - Reserved,
RES0.
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