ARM Cortex-A53 MPCore - Page 517

Embedded Trace Macrocell
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Table 13-12 shows the TRCTSCTLR bit assignments:
The TRCTSCTLR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x030 .
13.8.10 Synchronization Period Register
The TRCSYNCPR characteristics are:
Purpose Controls how often periodic trace synchronization requests occur.
Usage constraints • You must always program this register as part of trace unit
initialization.
• Accepts writes only when the trace unit is disabled.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-12 shows the TRCSYNCPR bit assignments.
Figure 13-12 TRCSYNCPR bit assignments
Table 13-13 shows the TRCSYNCPR bit assignments.
The TRCSYNCPR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x034 .
Table 13-12 TRCTSCTLR bit assignments
Bits Name Function
[31:8] - Reserved,
RES0
[7] TYPE Single or combined resource selector
[6:4] - Reserved
[3:1] SEL Identifies the resource selector to use
31 0
RES0
45
Period
Table 13-13 TRCSYNCPR bit assignments
Bits Name Function
[31:5] - Reserved,
RES0.
[4:0] PERIOD Defines the number of bytes of trace between synchronization requests as a total of the number of bytes generated
by both the instruction and data streams. The number of bytes is 2
N
where N is the value of this field:
• A value of zero disables these periodic synchronization requests, but does not disable other
synchronization requests.
• The minimum value that can be programmed, other than zero, is 8, providing a minimum synchronization
period of 256 bytes.
• The maximum value is 20, providing a maximum synchronization period of 2
20
bytes.