ARM Cortex-A53 MPCore - Page 518

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-23
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13.8.11 Cycle Count Control Register
The TRCCCCTLR characteristics are:
Purpose Sets the threshold value for cycle counting.
Usage constraints • Accepts writes only when the trace unit is disabled.
• Must be programmed if TRCCONFIGR.CCI==1.
• Minimum value that can be programmed is defined in
TRCIDR3.CCITMIN.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-13 shows the TRCCCCTLR bit assignments.
Figure 13-13 TRCCCCTLR bit assignments
Table 13-14 shows the TRCCCCTLR bit assignments.
The TRCCCCTLR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x038 .
13.8.12 Trace ID Register
The TRCTRACEIDR characteristics are:
Purpose Sets the trace ID for instruction trace.
Usage constraints • You must always program this register as part of trace unit
initialization.
• Accepts writes only when the trace unit is disabled.
Configurations Available in all configurations.
Attributes TRCTRACEIDR is a 32-bit RW trace register.
See the register summary in Table 13-3 on page 13-10.
Figure 13-14 shows the TRCTRACEIDR bit assignments.
Figure 13-14 TRCTRACEIDR bit Assignments
31 0
RES0 THRESHOLD
12 11
Table 13-14 TRCCCCTLR bit assignments
Bits Name Function
[31:12] - Reserved,
RES0.
[11:0] THRESHOLD Instruction trace cycle count threshold.
31 0
RES0 TRACEID
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