Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-24
ID021414 Non-Confidential
Table 13-15 shows the TRCTRACEIDR bit assignments.
The TRCTRACEIDR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x040
.
13.8.13 ViewInst Main Control Register
The TRCVICTLR characteristics are:
Purpose Controls instruction trace filtering.
Usage constraints • Accepts writes only when the trace unit is disabled.
• Returns stable data only when TRCSTATR.PMSTABLE==1.
• Must be programmed, particularly to set the value of the SSSTATUS
bit, that sets the state of the start-stop logic.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-15 shows the TRCVICTLR bit assignments.
Figure 13-15 TRCVICTLR bit assignments
Table 13-15 TRCTRACEIDR bit assignments
Bits Name Function
[31:7] - Reserved,
RES0.
[6:0] TRACEID Trace ID value.
When only instruction tracing is enabled, this provides the trace ID.
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