Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-25
ID021414 Non-Confidential
Table 13-16 shows the TRCVICTLR bit assignments.
Table 13-16 TRCVICTLR bit assignments
Bits Name Function
[31:24] - Reserved,
RES0.
[23:20] EXLEVEL_NS In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
exception level:
0
Trace unit generates instruction trace, in Non-secure state, for exception level n.
1
Trace unit does not generate instruction trace, in Non-secure state, for exception level n.
The exception levels are:
Bit[20] Exception level 0.
Bit[21] Exception level 1.
Bit[22] Exception level 2.
Bit[23] RAZ/WI. Instruction tracing is not implemented for exception level 3.
[19:16] EXLEVEL_S In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception
level:
0
Trace unit generates instruction trace, in Secure state, for exception level n.
1
Trace unit does not generate instruction trace, in Secure state, for exception level n.
The exception levels are:
Bit[16] Exception level 0.
Bit[17] Exception level 1.
Bit[18] RAZ/WI. Instruction tracing is not implemented for exception level 2.
Bit[19] Exception level 3.
[15:12] - Reserved, RES0.
[11] TRCERR Selects whether a system error exception must always be traced:
0
System error exception is traced only if the instruction or exception immediately before
the system error exception is traced.
1
System error exception is always traced regardless of the value of ViewInst.
[10] TRCRESET Selects whether a reset exception must always be traced:
0
Reset exception is traced only if the instruction or exception immediately before the reset
exception is traced.
1
Reset exception is always traced regardless of the value of ViewInst.
[9] SSSTATUS Indicates the current status of the start/stop logic:
0
Start/stop logic is in the stopped state.
1
Start/stop logic is in the started state.
[8] - Reserved,
RES0.
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