Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-27
ID021414 Non-Confidential
The TRCVIIECTLR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x084
.
13.8.15 ViewInst Start-Stop Control Register
The TRCVISSCTLR characteristics are:
Purpose Defines the single address comparators that control the ViewInst
Start/Stop logic.
Usage constraints • You must always program this register as part of trace unit
initialization.
• Accepts writes only when the trace unit is disabled.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-17 shows the TRCVISSCTLR bit assignments.
Figure 13-17 TRCVISSCTLR bit assignments
Table 13-18 shows the TRCVISSCTLR bit assignments.
The TRCVISSCTLR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x088
.
13.8.16 Sequencer State Transition Control Registers 0-2
The TRCSEQEVRn characteristics are:
Purpose Defines the sequencer transitions that progress to the next state or
backwards to the previous state. The ETM trace unit implements a
sequencer state machine with up to four states.
Usage constraints • Accepts writes only when the trace unit is disabled.
• Returns stable data only when TRCSTATR.PMSTABLE==1.
• Software must use this register to set the initial state of the sequencer
before the sequencer is used.
Configurations Available in all configurations.
Table 13-18 TRCVISSCTLR bit assignments
Bits Name Function
[31:24] - Reserved,
RES0.
[23:16] STOP Defines the single address comparators to stop trace with the ViewInst Start/Stop control.
One bit is provided for each implemented single address comparator.
[15:8] - Reserved,
RES0.
[7:0] START Defines the single address comparators to start trace with the ViewInst Start/Stop control.
One bit is provided for each implemented single address comparator.
To Next Page
Loading...
