ARM Cortex-A53 MPCore - Page 523

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-28
ID021414 Non-Confidential
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-18 shows the TRCSEQEVRn bit assignments.
Figure 13-18 TRCSEQEVRn bit assignments
Table 13-19 shows the TRCSEQEVRn bit assignments.
The TRCSEQEVRn registers can be accessed through the internal memory-mapped interface
and the external debug interface, offsets:
TRCSEQEVR0
0x100 .
TRCSEQEVR1
0x104 .
TRCSEQEVR2
0x108 .
13.8.17 Sequencer Reset Control Register
The TRCSEQRSTEVR characteristics are:
Purpose Resets the sequencer to state 0.
Usage constraints • Accepts writes only when the trace unit is disabled.
• If the sequencer is used, you must program all sequencer state
transitions with a valid event.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
31 0
RES 0
16
B SEL F SEL
15 8 7111214 436
B TYPE F TYPE
RES 0 RES 0
Table 13-19 TRCSEQEVRn bit assignments
Bits Name Function
[31:16] - Reserved,
RES0.
[15] B TYPE Selects the resource type to move backwards to this state from the next state:
0 Single selected resource.
1 Boolean combined resource pair.
[14:12] - Reserved,
RES0
[11:8] B SEL Selects the resource number, based on the value of B TYPE:
When B TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When B TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
[7] F TYPE Selects the resource type to move forwards from this state to the next state:
0 Single selected resource.
1 Boolean combined resource pair.
[6:4] - Reserved,
RES0.
[3:0] F SEL Selects the resource number, based on the value of F TYPE:
When F TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When F TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].