Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-29
ID021414 Non-Confidential
Figure 13-19 shows the TRCSEQRSTEVR bit assignments.
Figure 13-19 TRCSEQRSTEVR bit assignments
Table 13-20 shows the TRCSEQRSTEVR bit assignments.
The TRCSEQRSTEVR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x118
.
13.8.18 Sequencer State Register
The TRCSEQSTR characteristics are:
Purpose Holds the value of the current state of the sequencer.
Usage constraints • Accepts writes only when the trace unit is disabled.
• Returns stable data only when TRCSTATR.PMSTABLE==1.
• Software must use this register to set the initial state of the sequencer
before the sequencer is used.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-20 shows the TRCSEQSTR bit assignments.
Figure 13-20 TRCSEQSTR bit assignments
Table 13-20 TRCSEQRSTEVR bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7] RESETTYPE Selects the resource type to move back to state 0:
0
Single selected resource.
1
Boolean combined resource pair.
[6:4] - Reserved,
RES0.
[3:0] RESETSEL Selects the resource number, based on the value of RESETTYPE:
When RESETTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When RESETTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
To Next Page
Loading...
