ARM Cortex-A53 MPCore - Page 525

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-30
ID021414 Non-Confidential
Table 13-21 shows the TRCSEQSTR bit assignments.
The TRCSEQSTR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x11c .
13.8.19 External Input Select Register
The TRCEXTINSELR characteristics are:
Purpose Controls the selectors that choose an external input as a resource in the
ETM trace unit. You can use the Resource Selectors to access these
external input resources.
Usage constraints Accepts writes only when the trace unit is disabled.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-21 shows the TRCEXTINSELR bit assignments.
Figure 13-21 TRCEXTINSELR bit assignments
Table 13-22 shows the TRCEXTINSELR bit assignments.
Table 13-21 TRCSEQSTR bit assignments
Bits Name Function
[31:2] - Reserved,
RES0.
[1:0] STATE Current sequencer state:
b00 State 0.
b01 State 1.
b10 State 2.
b11 State 3.
31 08716 1524 23
SEL2 SEL1 SEL0SEL3
2829
RES0 RES0
2021
RES0
1213
RES0
45
Table 13-22 TRCEXTINSELR bit assignments
Bits Name Function
[31:29] - Reserved,
RES0.
[28:24] SEL3 Selects an event from the external input bus for External Input Resource 3.
[23:21] - Reserved,
RES0.
[20:16] SEL2 Selects an event from the external input bus for External Input Resource 2.
[15:13] - Reserved,
RES0.
[12:8] SEL1 Selects an event from the external input bus for External Input Resource 1.
[7:5] - Reserved,
RES0.
[4:0] SEL0 Selects an event from the external input bus for External Input Resource 0.