Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-32
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Table 13-24 shows the TRCCNTCTLR0 bit assignments.
The TRCCNTCTLR0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x150
.
13.8.22 Counter Control Register 1
The TRCCNTCTLR1 characteristics are:
Purpose Controls the counter.
Usage constraints Accepts writes only when the trace unit is disabled.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-24 shows the TRCCNTCTLR1 bit assignments.
Figure 13-24 TRCCNTCTLR1 bit assignments
Table 13-24 TRCCNTCTLR0 bit assignments
Bits Name Function
[31:17] - Reserved,
RES0.
[16] RLDSELF Defines whether the counter reloads when it reaches zero:
0
The counter does not reload when it reaches zero. The counter only reloads based on
RLDTYPE and RLDSEL.
1
The counter reloads when it reaches zero and the resource selected by CNTTYPE and
CNTSEL is also active. The counter also reloads based on RLDTYPE and RLDSEL.
[15] RLDTYPE Selects the resource type for the reload:
0
Single selected resource.
1
Boolean combined resource pair.
[14:12] - Reserved,
RES0.
[11:8] RLDSEL Selects the resource number, based on the value of RLDTYPE:
When RLDTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When RLDTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
[7] CNTTYPE Selects the resource type for the counter:
0
Single selected resource.
1
Boolean combined resource pair.
[6:4] - Reserved,
RES0.
[3:0] CNTSEL Selects the resource number, based on the value of CNTTYPE:
When CNTTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When CNTTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
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