ARM Cortex-A53 MPCore - Page 529

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-34
ID021414 Non-Confidential
Figure 13-25 shows the TRCCNTVRn bit assignments.
Figure 13-25 TRCCNTVRn bit assignments
Table 13-26 shows the TRCCNTVRn bit assignments.
The TRCCNTVRn registers can be accessed through the internal memory-mapped interface and
the external debug interface, offsets:
TRCCNTVR0
0x160 .
TRCCNTVR1
0x164 .
13.8.24 ID Register 8
The TRCIDR8 characteristics are:
Purpose Returns the maximum speculation depth of the instruction trace stream.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-26 shows the TRCIDR8 bit assignments.
Figure 13-26 TRCIDR8 bit assignments
Table 13-27 shows the TRCIDR8 bit assignments.
The TRCIDR8 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0x180 .
31 16 15 0
RES0 VALUE
Table 13-26 TRCCNTVRn bit assignments
Bits Value Function
[31:16] - Reserved,
RES0.
[15:0] VALUE Contains the current counter value.
31 0
MAXSPEC
Table 13-27 TRCIDR8 bit assignments
Bits Name Function
[31:0] MAXSPEC The maximum number of P0 elements in the trace stream that can be speculative at any time.
0 Maximum speculation depth of the instruction trace stream.