ARM Cortex-A53 MPCore - Page 542

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-47
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The TRCSSCCR0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x280 .
13.8.39 Single-Shot Comparator Status Register 0
The TRCSSCSR0 characteristics are:
Purpose Indicates the status of the single-shot comparator:
• TRCSSCSR0 is sensitive to instruction addresses.
Usage constraints • Accepts writes only when the trace unit is disabled.
• The STATUS bit value is stable only when
TRCSTATR.PMSTABLE==1.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-41 shows the TRCSSCSR0 bit assignments.
Figure 13-41 TRCSSCSR0 bit assignments
Table 13-42 shows the TRCSSCSR0 bit assignments.
[19:16] ARC Selects one or more address range comparators for single-shot control.
One bit is provided for each implemented address range comparator.
[15:8] - Reserved,
RES0.
[7:0] SAC Selects one or more single address comparators for single-shot control.
One bit is provided for each implemented single address comparator.
Table 13-41 TRCSSCCR0 bit assignments (continued)
Bits Name Function
31 30 3210
RES 0
STATUS DV
DA
INST
Table 13-42 TRCSSCSR0 bit assignments
Bits Name Function
[31] STATUS Single-shot status. This indicates whether any of the selected comparators have matched:
0 Match has not occurred.
1 Match has occurred at least once.
When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written
to 0 to enable this single-shot comparator control.
[30:3] - Reserved,
RES0.