ARM Cortex-A53 MPCore - Page 543

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-48
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The TRCSSCSR0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x2A0 .
13.8.40 OS Lock Access Register
The TRCOSLAR characteristics are:
Purpose Sets and clears the OS Lock, to lock out external debugger accesses to the
ETM trace unit registers.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-42 shows the TRCOSLAR bit assignments.
Figure 13-42 TRCOSLAR bit assignments
Table 13-43 shows the TRCOSLAR bit assignments.
The TRCOSLAR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x300 .
13.8.41 OS Lock Status Register
The TRCOSLSR characteristics are:
Purpose Returns the status of the OS Lock.
[2] DV Data value comparator support:
0 Single-shot data value comparisons not supported.
[1] DA Data address comparator support:
0 Single-shot data address comparisons not supported.
[0] INST Instruction address comparator support:
1 Single-shot instruction address comparisons supported.
Table 13-42 TRCSSCSR0 bit assignments (continued)
Bits Name Function
31 10
RES
0
OSLK
Table 13-43 TRCOSLAR bit assignments
Bits Name Function
[31:1] - TRCRSCTLR
N
[0] OSLK OS Lock key value:
0 Unlock the OS Lock.
1 Lock the OS Lock.