Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-50
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Figure 13-44 TRCPDCR bit assignments
Table 13-45 shows the TRCPDCR bit assignments.
The TRCPDCR can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0x310
.
13.8.43 Power Down Status Register
The TRCPDSR characteristics are:
Purpose Indicates the power down status of the ETM trace unit.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-45 shows the TRCPDSR bit assignments.
Figure 13-45 TRCPDSR bit assignments
Table 13-45 TRCPDCR bit assignments
Bits Name Function
[31:4] - Reserved,
RES0.
[3] PU Powerup request, to request that power to the ETM trace unit and access to the trace registers is
maintained:
0
Power not requested.
1
Power requested.
This bit is reset to 0 on a trace unit reset.
[2:0] - Reserved,
RES0.
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