Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-55
ID021414 Non-Confidential
Table 13-50 shows the TRCVMIDCVR0 bit assignments.
The TRCVMIDCVR0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x640
.
13.8.48 Context ID Comparator Control Register 0
The TRCCIDCCTLR0 characteristics are:
Purpose Controls the mask value for the context ID comparators.
Usage constraints • Accepts writes only when the trace unit is disabled.
• If software uses the TRCCIDCVRn registers, where n=0 to 3, then
it must program this register.
• If software sets a mask bit to 1 then it must program the relevant byte
in TRCCIDCVRn to
0x00
.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-50 shows the TRCCIDCCTLR0 bit assignments.
Figure 13-50 TRCCIDCCTLR0 bit assignments
Table 13-51 shows the TRCCIDCCTLR0 bit assignments.
The TRCCIDCCTLR0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x680
.
Table 13-50 TRCVMIDCVR0 bit assignments
Bits Name Function
[63:8] - Reserved,
RES0
[7:0] VALUE The VMID value
Table 13-51 TRCCIDCCTLR0 bit assignments
Bits Name Function
[31:4] - Reserved,
RES0.
[3:0] COMP0 Controls the mask value that the trace unit applies to TRCCIDCVR0. Each bit in this field corresponds to a byte
in TRCCIDCVR0. When a bit is:
0
The trace unit includes the relevant byte in TRCCIDCVR0 when it performs the Context ID
comparison.
1
The trace unit ignores the relevant byte in TRCCIDCVR0 when it performs the Context ID
comparison.
To Next Page
Loading...
