ARM Cortex-A53 MPCore - Page 554

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-59
ID021414 Non-Confidential
13.8.52 Integration Instruction ATB Out Register
The TRCITIATBOUTR characteristics are:
Purpose Sets the state of the output pins shown in Table 13-55.
Usage constraints • Available when bit[0] of TRCITCTRL is set to 1.
• The value of the register sets the signals on the output pins when the
register is written.
Configurations Available in all configurations.
Attributes See the register summaries in Table 13-3 on page 13-10.
Figure 13-54 shows the TRCITIATBOUTR bit assignments.
Figure 13-54 TRCITIATBOUTR bit assignments
Table 13-55 shows the TRCITIATBOUTR bit assignments.
The TRCITIATBOUTR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xEFC .
13.8.53 Integration Mode Control Register
The TRCITCTRL characteristics are:
Purpose Enables topology detection or integration testing, by putting the ETM
trace unit into integration mode.
Usage constraints ARM recommends that you perform a debug reset after using integration
mode.
Configurations Available in all configurations.
31 0
AFREADY
Reserved
21
ATVALID
87910
BYTES
Reserved
Table 13-55 TRCITIATBOUTR bit assignments
Bits Name Function
[31:10] - Reserved. Read undefined.
[9:8] BYTES
Drives the ATBYTESMn[1:0] output pins
a
.
a. When a bit is set to 0, the corresponding output pin is LOW.
When a bit is set to 1, the corresponding output pin is HIGH.
The TRCITIATBOUTR bit values always correspond to the physical
state of the output pins.
[7:2] - Reserved. Read undefined.
[1] AFREADY
Drives the AFREADYMn output pin
a
.
[0] ATVALID
Drives the ATVALIDMn output pin
a
.